Solution Manual for VHDL for Engineers Kenneth L. Short

This is completed downloadable of Solution Manual for VHDL for Engineers Kenneth L. Short

 

Product Details:

• ISBN-10 ‏ : ‎ 0131424785
• ISBN-13 ‏ : ‎ 978-0131424784
• Author: Kenneth L. Short
• VHDL for Engineers, First Edition is perfect for anyone with a basic understanding of logic design and a minimal background in programming who desires to learn how to design digital systems using VHDL. No prior experience with VHDL is required. This text teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.

 

Table of Content:

1. 1 Digital Design Using VHDL and PLDs
2. 1.1 VHDL/PLD Design Methodology
3. 1.2 Requirements Analysis and Specification
4. 1.3 VHDL Design Description
5. 1.4 Verification Using Simulation
6. 1.5 Testbenches
7. 1.6 Functional (Behavioral) Simulation
8. 1.7 Programmable Logic Devices (PLDs)
9. 1.8 SPLDs and the 22V10
10. 1.9 Logic Synthesis for the Target PLD
11. 1.10 Place-and-Route and Timing Simulation
12. 1.11 Programming and Verifying a Target PLD
13. 1.12 VHDL/PLD Design Methodology Advantages
14. 1.13 VHDL’s Development
15. 1.14 VHDL for Synthesis versus VHDL for Simulation
16. 1.15 This Book’s Primary Objective
17. 2 Entities, Architectures, and Coding Styles
18. 2.1 Design Units, Library Units, and Design Entities
19. 2.2 Entity Declaration
20. 2.3 VHDL Syntax Definitions
21. 2.4 Port Modes
22. 2.5 Architecture Body
23. 2.6 Coding Styles
24. 2.7 Synthesis Results versus Coding Style
25. 2.8 Levels of Abstraction and Synthesis
26. 2.9 Design Hierarchy and Structural Style
27. 3 Signals and Data Types
28. 3.1 Object Classes and Object Types
29. 3.2 Signal Objects
30. 3.3 Scalar Types
31. 3.4 Type Std_Logic
32. 3.5 Scalar Literals and Scalar Constants
33. 3.6 Composite Types
34. 3.7 Arrays
35. 3.8 Types Unsigned and Signed
36. 3.9 Composite Literals and Composite Constants
37. 3.10 Integer Types
38. 3.11 Port Types for Synthesis
39. 3.12 Operators and Expressions
40. 4 Dataflow Style Combinational Design
41. 4.1 Logical Operators
42. 4.2 Signal Assignments in Dataflow Style Architectures
43. 4.3 Selected Signal Assignment
44. 4.4 Type Boolean and the Relational Operators
45. 4.5 Conditional Signal Assignment
46. 4.6 Priority Encoders
47. 4.7 Don’t Care Inputs and Outputs
48. 4.8 Decoders
49. 4.9 Table Lookup
50. 4.10 Three-state Buffers
51. 4.11 Avoiding Combinational Loops
52. 5 Behavioral Style Combinational Design
53. 5.1 Behavioral Style Architecture
54. 5.2 Process Statement
55. 5.3 Sequential Statements
56. 5.4 Case Statement
57. 5.5 If Statement
58. 5.6 Loop Statement
59. 5.7 Variables
60. 5.8 Parity Detector Example
61. 5.9 Synthesis of Processes Describing Combinational Systems
62. 6 Event-Driven Simulation
63. 6.1 Simulator Approaches
64. 6.2 Elaboration
65. 6.3 Signal Drivers
66. 6.4 Simulator Kernel Process
67. 6.5 Simulation Initialization
68. 6.6 Simulation Cycles
69. 6.7 Signals versus Variables
70. 6.8 Delta Delays
71. 6.9 Delta Delays and Combinational Feedback
72. 6.10 Multiple Drivers
73. 6.11 Signal Attributes
74. 7 Testbenches for Combinational Designs
75. 7.1 Design Verification
76. 7.2 Functional Verification of Combinational Designs
77. 7.3 A Simple Testbench
78. 7.4 Physical Types
79. 7.5 Single Process Testbench
80. 7.6 Wait Statements
81. 7.7 Assertion and Report Statements
82. 7.8 Records and Table Lookup Testbenches
83. 7.9 Testbenches That Compute Stimulus and Expected Results
84. 7.10 Predefined Shift Operators
85. 7.11 Stimulus Order Based on UUT Functionality
86. 7.12 Comparing a UUT to a Behavioral Intent Model
87. 7.13 Code Coverage and Branch Coverage
88. 7.14 Post-Synthesis and Timing Verifications for Combinational Designs
89. 7.15 Timing Models Using VITAL and SDF
90. 8 Latches and Flip-flops
91. 8.1 Sequential Systems and Their Memory Elements
92. 8.2 D Latch
93. 8.3 Detecting Clock Edges
94. 8.4 D Flip-flops
95. 8.5 Enabled (Gated) Flip-flop
96. 8.6 Other Flip-flop Types
97. 8.7 PLD Primitive Memory Elements
98. 8.8 Timing Requirements and Synchronous Input Data
99. 9 Multibit Latches, Registers, Counters, and Memory
100. 9.1 Multibit Latches and Registers
101. 9.2 Shift Registers
102. 9.3 Shift Register Counters
103. 9.4 Counters
104. 9.5 Detecting Non-clock Signal Edges
105. 9.6 Microprocessor Compatible Pulse Width Modulated Signal Generator
106. 9.7 Memories
107. 10 Finite State Machines
108. 10.1 Finite State Machines
109. 10.2 FSM State Diagrams
110. 10.3 Three Process FSM VHDL Template
111. 10.4 State Diagram Development
112. 10.5 Decoder for an Optical Shaft Encoder
113. 10.6 State Encoding and State Assignment
114. 10.7 Supposedly Safe FSMs
115. 10.8 Inhibit Logic FSM Example
116. 10.9 Counters as Moore FSMs
117. 11 ASM Charts and RTL Design
118. 11.1 Algorithmic State Machine Charts
119. 11.2 Converting ASM Charts to VHDL
120. 11.3 System Architecture
121. 11.4 Successive Approximation Register Design Example
122. 11.5 Sequential Multiplier Design
123. 12 Subprograms
124. 12.1 Subprograms
125. 12.2 Functions
126. 12.3 Procedures
127. 12.4 Array Attributes and Unconstrained Arrays
128. 12.5 Overloading Subprograms and Operators
129. 12.6 Type Conversions
130. 13 Packages
131. 13.1 Packages and Package Bodies
132. 13.2 Standard and De Facto Standard Packages
133. 13.3 Package STD_LOGIC_1164
134. 13.4 Package NUMERIC_STD (IEEE Std 1076.3)
135. 13.5 Package STD_LOGIC_ARITH
136. 13.6 Packages for VHDL Text Output
137. 14 Testbenches for Sequential Systems
138. 14.1 Simple Sequential Testbenches
139. 14.2 Generating a System Clock
140. 14.3 Generating the System Reset
141. 14.4 Synchronizing Stimulus Generation and Monitoring
142. 14.5 Testbench for Successive Approximation Register
143. 14.6 Determining a Testbench Stimulus for a Sequential System
144. 14.7 Using Procedures for Stimulus Generation
145. 14.8 Output Verification in Stimulus Procedures
146. 14.9 Bus Functional Models
147. 14.10 Response Monitors
148. 15 Modular Design and Hierarchy
149. 15.1 Modular Design, Partitioning, and Hierarchy
150. 15.2 Design Units and Library Units
151. 15.3 Design Libraries
152. 15.4 Using Library Units
153. 15.5 Direct Design Entity Instantiation
154. 15.6 Components and Indirect Design Entity Instantiation
155. 15.7 Configuration Declarations
156. 15.8 Component Connections
157. 15.9 Parameterized Design Entities
158. 15.10 Library of Parameterized Modules (LPM)
159. 15.11 Generate Statement
160. 16 More Design Examples
161. 16.1 Microprocessor-Compatible Quadrature Decoder/Counter Design
162. 16.2 Verification of Quadrature Decoder/Counter
163. 16.3 Parameterized Quadrature Decoder/Counter
164. 16.4 Electronic Safe Design
165. 16.5 Verification of Electronic Safe
166. 16.6 Encoder for RF Transmitter Design
167. Appendix VHDL Attribute
168. Bibliography
169. Index